The present invention relates to a memory device, and more particularly to a memory device capable of obtaining a sufficient timing margin for a corresponding internal operation after receiving and decoding an external command and an address.
A semiconductor memory device is a kind of data storage. When a data is required by a data processor such as a central processing unit (CPU), the semiconductor memory device outputs the data corresponding to an address received from the data processor, or stores the data provided by the data processor in a position corresponding to the address.
As semiconductor integration technology advances and an operation speed of a system including semiconductor devices increases, there has been a demand for a more rapid semiconductor memory device. In order to increase operation speed and stability of a semiconductor memory device, internal circuits of the semiconductor memory device need to operate rapidly and transfer signals or data rapidly.
An operation of a semiconductor memory device may be delayed by control circuits for reading data stored in a unit cell or transferring data to the unit cell, and by connecting lines or connecting apparatuses for transferring the data. In addition, the operation may also be delayed while the data output from the semiconductor memory device is transferred to the apparatus requiring the data in the system. The delay in a high speed system may degrade system performance and may lower system stability and system reliability. The length of the delay in a data transfer path may possibly vary with operation conditions, which may have a bad influence upon the performance of the semiconductor memory device.
In general, as a data output is performed rapidly after receiving a read command in a read operation, the performance of a semiconductor memory device also improves. In particular, the time required to output data is as an important performance index of a semiconductor memory device used in graphics where a large amount of data such as image data are processed at high speed. As described above, the semiconductor memory device needs to operate more rapidly although its internal operations become more complicated. If the internal operations are not performed in time, the reliability of the semiconductor memory device will be lost.
FIG. 1A is a timing diagram of a read operation performed by a typical semiconductor memory device.
Referring to FIG. 1A, a read command RD input thereinto is decoded to generate a column selection signal YI. FIG. 1A shows a semiconductor memory device having a column address strobe (CAS) latency CL of 8, which means that data starts to be output from the semiconductor memory device through a data pad after 8 cycles of a system clock CLK/CLK# from when a read command RD was input thereinto.
Typically, the semiconductor memory device decodes the read command RD to activate an internal read command INTERNAL_RD and simultaneously activate a read column access signal CASP6RD and a read address latch strobe signal CASP6RD_ADD at the same time. The activation of the read column access signal CASP6RD and the read address latch strobe signal CASP6RD_ADD is synchronized with the system clock CLK/CLK# which serves as a reference in applying the address and the read command RD to the semiconductor memory device. Accordingly, a column address signal ADDRESS<3:8> generated by the read address latch strobe signal CASP6RD_ADD is activated at the time when the read column access signal CASP6RD is activated.
In more detail, the column address signals ADDRESS<3:8> each is generated after 1 tCK, i.e. after one cycle of the system clock, from when the read command RD was input. The column address signal ADDRESS<3:8> has an effective pulse width of 2 tCK according to a minimum interval tCCD between the read commands RD. Similarly, the read column access signal CASP6RD for generating the column selection signal YI is also generated after 1 tCK from when the read command RD was input, i.e., at the time when the column address signal ADDRESS<3:8> was generated. The read column access signal CASP6RD has a pulse width of 1 tCK, which is the same as that of the column selection signal YI.
The read column access signal CASP6RD is decoded to generate a column strobe signal STROBE. The column address signal ADDRESS<3:8> is decoded to generate a bank address BANK_ADD. The column pre-decoder and the column decoder generate a column selection signal YI in response to the column strobe signal STROBE and the bank address BANK_ADD to control a unit cell of a bank corresponding to the address received from outside. The column strobe signal STROBE corresponds to a command received from outside, and the bank address BANK_ADD corresponds to an address received from outside. A circuit outputting the column strobe signal STROBE into the column pre-decoder is different from that outputting the bank address BANK_ADD thereinto. That is, a circuit for decoding an external address received from outside to generate an internal address signal controlling an internal unit cell is different from a circuit for decoding an external command received from outside to generate an internal command signal controlling an internal operation corresponding to the external command.
As described above, the external command and the external address are decoded and are input into a column decoding circuit through different circuits. In other words, the internal command signal and the internal address are generated in different circuits. Accordingly, it is difficult to input the internal command signal and the internal address signal such as a column strobe signal STROBE and a bank address signal BANK_ADD into the column decoding circuit at the same time. Accordingly, an activation of the column strobe signal STROBE and an activation of the bank address may disagree with each other when they are input into the column pre-decoder. This may results in difficulties in determining an exact activation time of the column selection signal YI corresponding to the column strobe signal STROBE and the bank address signal BANK_ADD, and in providing a sufficient pulse width.
FIG. 1B is a timing diagram of a write operation performed by a typical semiconductor memory device. Referring to FIG. 1B, after a write latency WL from when a write command WT was input into the semiconductor memory device, a data is input thereinto through a data pad to be stored in a unit cell of the semiconductor memory device. FIG. 1B shows, for example, a semiconductor memory device when a write latency WL is 4 and a burst length BL is 8.
A data starts to be input into the semiconductor memory device after the write latency WL from when a write command WT was input into the semiconductor memory device. During the clock cycles corresponding to the burst length BL from then, the data is input into the semiconductor memory device. After 1 tCK from then, a write column access signal CASP6WT and a write address latch strobe signal CASP6WT_ADD are simultaneously generated. The write address latch strobe signal CASP6WT_ADD and a column address signal ADDRESS<3:8> generated thereby are input into the column decoding circuit at the same time in synchronization with the system clock CLK/CLK# which serves as a reference in applying the address and the write command WT.
The write operation is similar to the read operation in that signals such as a write column access signal CASP6WT and a column selection signal YI has an active region of a width of 1 tCK, and the column address signal ADDRESS<3:8> has an effective window of a width of 2 tCK. However, the write operation differs from the read operation in that internal operations start after 1 tCK from receiving all corresponding data instead of starting after 1 tCK from when the write command WT was received.
Similarly to the read operation, a circuit generating a column strobe signal STROBE in response to a write column access signal CASP6WT is different from a circuit generating a bank address signal BANK_ADD in response to a column address signal ADDRESS<3:8>. Therefore, it is also difficult to input an internal command signal generated in response to the external command and an internal address signal generated in response to the external address such as the column strobe signal STROBE and the bank address signal BANK_ADD into the column decoding circuit at the same time.
In order to generate a column selection signal YI using a column strobe signal STROBE and a bank address signal BANK_ADD which are input at different times, an additional delay or synchronization circuit is required to control the column strobe signal STROBE and the bank address signal BANK_ADD. That is, input times of the column strobe signal STROBE and the bank address signal BANK_ADD are controlled to stabilize an activation time and an active region of a column selection signal YI. However, such a control greatly affects an address access time tAA. In addition, accuracy of such a control is greatly affected by operation conditions such as a process, a voltage level and a temperature. Accordingly, in a high speed semiconductor memory device such as a GDDR5 and DDR4, a timing margin for an internal operation in response to read and write commands received from outside may be reduced.
The above described method for decoding an external command and an external address to input them into internal circuits of a semiconductor memory device is a method for simultaneously generating an internal signal corresponding to the external command and that corresponding to the external address on the basis of the system clock. That is, when a CAS command for the external address and the external command is input into the semiconductor memory device, the column address signal ADDRESS<3:8> and the read or write column access signal CASP6RD or CASP6WT are simultaneously generated. However, as described above, the column address signal ADDRESS<3:8> and the read or write column access signal CASP6RD or CASP6WT are input into the column decoding circuit through different circuit paths. In addition, configurations and operations of the circuits for decoding respective signals and generating respective internal signals are different from each other. Therefore, the signals are input at different times into the column decoding circuit. This results in difficulty in guaranteeing an operational reliability when the semiconductor memory device operates at high speed.